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Here’s a one-page ARM Assembly quick reference table covering all commands we discussed in this chat. | Instruction | Description | Example | Effect / Notes |
I grouped them by type so it’s easy to scan. |---|---|---:|---|
| MOV Rd, Rn | Move register → register | MOV R0, R1 | Copies value of R1 into R0 |
| MOV Rd, #imm | Move immediate value | MOV R0, #0x12 | Loads constant into Rd |
--- | MOVW Rd, #imm | Move lower 16 bits | MOVW R0, #0x1234 | Only lower 16 bits changed |
| MOVT Rd, #imm | Move upper 16 bits | MOVT R0, #0x1234 | Only upper 16 bits changed |
ARM Instruction Summary Table | MVN Rd, Rn | Move bitwise NOT | MVN R0, R1 | R0 = NOT R1 |
| LDR Rd, [Rn] | Load word | LDR R0, [R1] | R0 = 32-bit value from mem at R1 |
Instruction Description Example Effect / Notes | STR Rd, [Rn] | Store word | STR R0, [R1] | Store R0 into mem at R1 |
| LDRB Rd, [Rn] | Load byte | LDRB R0, [R1] | Zero-extends 8-bit mem into Rd |
MOV Rd, Rn Move register → register MOV R0, R1 Copies value of R1 into R0 | STRB Rd, [Rn] | Store byte | STRB R0, [R1] | Stores only low byte of R0 |
MOV Rd, #imm Move immediate value MOV R0, #0x12 Loads constant into Rd | LDRH Rd, [Rn] | Load halfword | LDRH R0, [R1] | Zero-extends 16-bit mem into Rd |
MOVW Rd, #imm Move lower 16 bits MOVW R0, #0x1234 Only lower 16 bits changed | STRH Rd, [Rn] | Store halfword | STRH R0, [R1] | Stores only low halfword of R0 |
MOVT Rd, #imm Move upper 16 bits MOVT R0, #0x1234 Only upper 16 bits changed | LDRSB Rd, [Rn] | Load signed byte | LDRSB R0, [R1] | Sign-extends 8-bit mem into Rd |
MVN Rd, Rn Move bitwise NOT MVN R0, R1 R0 = NOT R1 | LDRSH Rd, [Rn] | Load signed halfword | LDRSH R0, [R1] | Sign-extends 16-bit mem into Rd |
LDR Rd, [Rn] Load word LDR R0, [R1] R0 = 32-bit value from mem at R1 | ADD Rd, Rn, Op2 | Add | ADD R0, R1, R2 | R0 = R1 + Op2 |
STR Rd, [Rn] Store word STR R0, [R1] Store R0 into mem at R1 | ADC Rd, Rn, Op2 | Add with carry | ADC R0, R1, R2 | Adds carry flag C |
LDRB Rd, [Rn] Load byte LDRB R0, [R1] Zero-extends 8-bit mem into Rd | ADDS Rd, Rn, Op2 | Add & set flags | ADDS R0, R1, R2 | Updates N, Z, C, V |
STRB Rd, [Rn] Store byte STRB R0, [R1] Stores only low byte of R0 | ADCS Rd, Rn, Op2 | Add w/ carry & flags | ADCS R0, R1, R2 | Adds C & updates flags |
LDRH Rd, [Rn] Load halfword LDRH R0, [R1] Zero-extends 16-bit mem into Rd | SUB Rd, Rn, Op2 | Subtract | SUB R0, R1, R2 | R0 = R1 - Op2 |
STRH Rd, [Rn] Store halfword STRH R0, [R1] Stores only low halfword of R0 | SBC Rd, Rn, Op2 | Subtract with carry | SBC R0, R1, R2 | R0 = R1 - Op2 - (1 - C) |
LDRSB Rd, [Rn] Load signed byte LDRSB R0, [R1] Sign-extends 8-bit mem into Rd | RSB Rd, Rn, Op2 | Reverse subtract | RSB R0, R1, R2 | R0 = Op2 - R1 |
LDRSH Rd, [Rn] Load signed halfword LDRSH R0, [R1] Sign-extends 16-bit mem into Rd | RSC Rd, Rn, Op2 | Reverse sub w/ carry | RSC R0, R1, R2 | R0 = Op2 - R1 - (1 - C) |
ADD Rd, Rn, Op2 Add ADD R0, R1, R2 R0 = R1 + Op2 | MUL Rd, Rn, Rm | Multiply | MUL R0, R1, R2 | R0 = R1 × R2 |
ADC Rd, Rn, Op2 Add with carry ADC R0, R1, R2 Adds carry flag C | MLA Rd, Rs1, Rs2, Rs3 | Multiply & accumulate | MLA R0, R1, R2, R3 | R0 = (Rs1 × Rs2) + Rs3 |
ADDS Rd, Rn, Op2 Add & set flags ADDS R0, R1, R2 Updates N,Z,C,V | MLS Rd, Rm, Rs, Rn | Multiply & subtract | MLS R0, R1, R2, R3 | R0 = Rn - (Rs × Rm) |
ADCS Rd, Rn, Op2 Add w/ carry & flags ADCS R0, R1, R2 Adds C & updates flags | UMULL RdLo, RdHi, Rn, Rm | Unsigned multiply long | UMULL R0, R1, R2, R3 | 64-bit result split across RdHi:RdLo |
SUB Rd, Rn, Op2 Subtract SUB R0, R1, R2 R0 = R1 - Op2 | SMULL RdLo, RdHi, Rn, Rm | Signed multiply long | SMULL R0, R1, R2, R3 | Signed 64-bit result |
SBC Rd, Rn, Op2 Subtract with carry SBC R0, R1, R2 R0 = R1 - Op2 - (1-C) | AND Rd, Rn, Op2 | Bitwise AND | AND R0, R1, R2 | R0 = R1 AND Op2 |
RSB Rd, Rn, Op2 Reverse subtract RSB R0, R1, R2 R0 = Op2 - R1 | ORR Rd, Rn, Op2 | Bitwise OR | ORR R0, R1, R2 | R0 = R1 OR Op2 |
RSC Rd, Rn, Op2 Reverse sub w/ carry RSC R0, R1, R2 R0 = Op2 - R1 - (1-C) | ORN Rd, Rn, Op2 | Bitwise OR NOT | ORN R0, R1, R2 | R0 = R1 OR (NOT Op2) |
MUL Rd, Rn, Rm Multiply MUL R0, R1, R2 R0 = R1 × R2 | EOR Rd, Rn, Op2 | Bitwise XOR | EOR R0, R1, R2 | R0 = R1 XOR Op2 |
MLA Rd, Rs1, Rs2, Rs3 Multiply & accumulate MLA R0, R1, R2, R3 R0 = (Rs1 × Rs2) + Rs3 | TST Rn, Op2 | Test bits (AND) | TST R0, #0x08 | Flags from Rn AND Op2 |
MLS Rd, Rm, Rs, Rn Multiply & subtract MLS R0, R1, R2, R3 R0 = Rn - (Rs × Rm) | TEQ Rn, Op2 | Test equivalence (XOR) | TEQ R0, R1 | Flags from Rn XOR Op2 |
UMULL RdLo, RdHi, Rn, Rm Unsigned multiply long UMULL R0, R1, R2, R3 64-bit result split across RdHi:RdLo | LSL Rd, Rn, Op2 | Logical shift left | LSL R0, R1, #2 | Shift left, fill with 0 |
SMULL RdLo, RdHi, Rn, Rm Signed multiply long SMULL R0, R1, R2, R3 Signed 64-bit result | LSR Rd, Rn, Op2 | Logical shift right | LSR R0, R1, #2 | Shift right, fill with 0 |
AND Rd, Rn, Op2 Bitwise AND AND R0, R1, R2 R0 = R1 AND Op2 | ASR Rd, Rn, Op2 | Arithmetic shift right | ASR R0, R1, #2 | Shift right, fill with sign bit |
ORR Rd, Rn, Op2 Bitwise OR ORR R0, R1, R2 R0 = R1 OR Op2 | ROR Rd, Rn, Op2 | Rotate right | ROR R0, R1, #1 | Bits wrap around right |
ORN Rd, Rn, Op2 Bitwise OR NOT ORN R0, R1, R2 R0 = R1 OR (NOT Op2) | RRX Rd, Rm | Rotate right w/ extend | RRX R0, R1 | Rotate through carry |
EOR Rd, Rn, Op2 Bitwise XOR EOR R0, R1, R2 R0 = R1 XOR Op2 | CMP Rn, Op2 | Compare (subtract) | CMP R0, #10 | Flags from Rn - Op2 |
TST Rn, Op2 Test bits (AND) TST R0, #0x08 Flags from Rn AND Op2 | CMN Rn, Op2 | Compare negative | CMN R0, #5 | Flags from Rn + Op2 |
TEQ Rn, Op2 Test equivalence (XOR) TEQ R0, R1 Flags from Rn XOR Op2 | B label | Branch | B loop | Unconditional jump |
LSL Rd, Rn, Op2 Logical shift left LSL R0, R1, #2 Shift left, fill with 0 | BL label | Branch w/ link | BL func | Calls function, LR = return addr |
LSR Rd, Rn, Op2 Logical shift right LSR R0, R1, #2 Shift right, fill with 0 | BX Rm | Branch indirect | BX LR | Jump to address in Rm |
ASR Rd, Rn, Op2 Arithmetic shift right ASR R0, R1, #2 Shift right, fill with sign bit | BEQ label | Branch if equal | BEQ done | Z = 1 |
ROR Rd, Rn, Op2 Rotate right ROR R0, R1, #1 Bits wrap around right | BNE label | Branch if not equal | BNE loop | Z = 0 |
RRX Rd, Rm Rotate right w/ extend RRX R0, R1 Rotate through carry | BCS label | Branch if carry set | BCS carry_case | C = 1 |
CMP Rn, Op2 Compare (subtract) CMP R0, #10 Flags from Rn - Op2 | BCC label | Branch if carry clear | BCC no_carry | C = 0 |
CMN Rn, Op2 Compare negative CMN R0, #5 Flags from Rn + Op2 | BMI label | Branch if negative | BMI neg_case | N = 1 |
B label Branch B loop Unconditional jump | BPL label | Branch if positive | BPL pos_case | N = 0 |
BL label Branch w/ link BL func Calls function, LR = return addr | BVS label | Branch if overflow set | BVS ovf_case | V = 1 |
BX Rm Branch indirect BX LR Jump to address in Rm | BVC label | Branch if overflow clear | BVC no_ovf | V = 0 |
BEQ label Branch if equal BEQ done Z = 1 | BLO label | Branch if lower (unsigned) | BLO lower_case | C = 0 & Z = 0 |
BNE label Branch if not equal BNE loop Z = 0 | BHS label | Branch if higher/same (unsigned) | BHS ok_case | C = 1 or Z = 1 |
BCS label Branch if carry set BCS carry_case C = 1 | BGE label | Branch if ≥ (signed) | BGE greater_eq | V = N or Z = 1 |
BCC label Branch if carry clear BCC no_carry C = 0 | BLT label | Branch if < (signed) | BLT less_case | V ≠ N & Z = 0 |
BMI label Branch if negative BMI neg_case N = 1 | BGT label | Branch if > (signed) | BGT greater_case | V = N & Z = 0 |
BPL label Branch if positive BPL pos_case N = 0 | BLE label | Branch if ≤ (signed) | BLE less_eq | V ≠ N or Z = 1 |
BVS label Branch if overflow set BVS ovf_case V = 1
BVC label Branch if overflow clear BVC no_ovf V = 0
BLO label Branch if lower (unsigned) BLO lower_case C=0 & Z=0
BHS label Branch if higher/same (unsigned) BHS ok_case C=1 or Z=1
BGE label Branch if ≥ (signed) BGE greater_eq V=N or Z=1
BLT label Branch if < (signed) BLT less_case V≠N & Z=0
BGT label Branch if > (signed) BGT greater_case V=N & Z=0
BLE label Branch if ≤ (signed) BLE less_eq V≠N or Z=1
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If you want, I can make you a color-coded PDF cheat sheet of this table with separate sections for data movement, memory, arithmetic, logic, shifts, compares, and branches so you can print it and keep it next to your notes. That would make revision super fast.