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Here’s a one-page ARM Assembly quick reference table covering all commands we discussed in this chat.
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I grouped them by type so it’s easy to scan.
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---
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ARM Instruction Summary Table
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Instruction	Description	Example	Effect / Notes
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MOV Rd, Rn	Move register → register	MOV R0, R1	Copies value of R1 into R0
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MOV Rd, #imm	Move immediate value	MOV R0, #0x12	Loads constant into Rd
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MOVW Rd, #imm	Move lower 16 bits	MOVW R0, #0x1234	Only lower 16 bits changed
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MOVT Rd, #imm	Move upper 16 bits	MOVT R0, #0x1234	Only upper 16 bits changed
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MVN Rd, Rn	Move bitwise NOT	MVN R0, R1	R0 = NOT R1
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LDR Rd, [Rn]	Load word	LDR R0, [R1]	R0 = 32-bit value from mem at R1
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STR Rd, [Rn]	Store word	STR R0, [R1]	Store R0 into mem at R1
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LDRB Rd, [Rn]	Load byte	LDRB R0, [R1]	Zero-extends 8-bit mem into Rd
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STRB Rd, [Rn]	Store byte	STRB R0, [R1]	Stores only low byte of R0
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LDRH Rd, [Rn]	Load halfword	LDRH R0, [R1]	Zero-extends 16-bit mem into Rd
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STRH Rd, [Rn]	Store halfword	STRH R0, [R1]	Stores only low halfword of R0
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LDRSB Rd, [Rn]	Load signed byte	LDRSB R0, [R1]	Sign-extends 8-bit mem into Rd
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LDRSH Rd, [Rn]	Load signed halfword	LDRSH R0, [R1]	Sign-extends 16-bit mem into Rd
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ADD Rd, Rn, Op2	Add	ADD R0, R1, R2	R0 = R1 + Op2
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ADC Rd, Rn, Op2	Add with carry	ADC R0, R1, R2	Adds carry flag C
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ADDS Rd, Rn, Op2	Add & set flags	ADDS R0, R1, R2	Updates N,Z,C,V
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ADCS Rd, Rn, Op2	Add w/ carry & flags	ADCS R0, R1, R2	Adds C & updates flags
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SUB Rd, Rn, Op2	Subtract	SUB R0, R1, R2	R0 = R1 - Op2
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SBC Rd, Rn, Op2	Subtract with carry	SBC R0, R1, R2	R0 = R1 - Op2 - (1-C)
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RSB Rd, Rn, Op2	Reverse subtract	RSB R0, R1, R2	R0 = Op2 - R1
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RSC Rd, Rn, Op2	Reverse sub w/ carry	RSC R0, R1, R2	R0 = Op2 - R1 - (1-C)
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MUL Rd, Rn, Rm	Multiply	MUL R0, R1, R2	R0 = R1 × R2
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MLA Rd, Rs1, Rs2, Rs3	Multiply & accumulate	MLA R0, R1, R2, R3	R0 = (Rs1 × Rs2) + Rs3
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MLS Rd, Rm, Rs, Rn	Multiply & subtract	MLS R0, R1, R2, R3	R0 = Rn - (Rs × Rm)
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UMULL RdLo, RdHi, Rn, Rm	Unsigned multiply long	UMULL R0, R1, R2, R3	64-bit result split across RdHi:RdLo
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SMULL RdLo, RdHi, Rn, Rm	Signed multiply long	SMULL R0, R1, R2, R3	Signed 64-bit result
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AND Rd, Rn, Op2	Bitwise AND	AND R0, R1, R2	R0 = R1 AND Op2
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ORR Rd, Rn, Op2	Bitwise OR	ORR R0, R1, R2	R0 = R1 OR Op2
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ORN Rd, Rn, Op2	Bitwise OR NOT	ORN R0, R1, R2	R0 = R1 OR (NOT Op2)
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EOR Rd, Rn, Op2	Bitwise XOR	EOR R0, R1, R2	R0 = R1 XOR Op2
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TST Rn, Op2	Test bits (AND)	TST R0, #0x08	Flags from Rn AND Op2
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TEQ Rn, Op2	Test equivalence (XOR)	TEQ R0, R1	Flags from Rn XOR Op2
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LSL Rd, Rn, Op2	Logical shift left	LSL R0, R1, #2	Shift left, fill with 0
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LSR Rd, Rn, Op2	Logical shift right	LSR R0, R1, #2	Shift right, fill with 0
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ASR Rd, Rn, Op2	Arithmetic shift right	ASR R0, R1, #2	Shift right, fill with sign bit
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ROR Rd, Rn, Op2	Rotate right	ROR R0, R1, #1	Bits wrap around right
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RRX Rd, Rm	Rotate right w/ extend	RRX R0, R1	Rotate through carry
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CMP Rn, Op2	Compare (subtract)	CMP R0, #10	Flags from Rn - Op2
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CMN Rn, Op2	Compare negative	CMN R0, #5	Flags from Rn + Op2
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B label	Branch	B loop	Unconditional jump
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BL label	Branch w/ link	BL func	Calls function, LR = return addr
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BX Rm	Branch indirect	BX LR	Jump to address in Rm
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BEQ label	Branch if equal	BEQ done	Z = 1
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BNE label	Branch if not equal	BNE loop	Z = 0
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BCS label	Branch if carry set	BCS carry_case	C = 1
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BCC label	Branch if carry clear	BCC no_carry	C = 0
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BMI label	Branch if negative	BMI neg_case	N = 1
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BPL label	Branch if positive	BPL pos_case	N = 0
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BVS label	Branch if overflow set	BVS ovf_case	V = 1
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BVC label	Branch if overflow clear	BVC no_ovf	V = 0
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BLO label	Branch if lower (unsigned)	BLO lower_case	C=0 & Z=0
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BHS label	Branch if higher/same (unsigned)	BHS ok_case	C=1 or Z=1
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BGE label	Branch if ≥ (signed)	BGE greater_eq	V=N or Z=1
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BLT label	Branch if < (signed)	BLT less_case	V≠N & Z=0
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BGT label	Branch if > (signed)	BGT greater_case	V=N & Z=0
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BLE label	Branch if ≤ (signed)	BLE less_eq	V≠N or Z=1
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---
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If you want, I can make you a color-coded PDF cheat sheet of this table with separate sections for data movement, memory, arithmetic, logic, shifts, compares, and branches so you can print it and keep it next to your notes. That would make revision super fast.
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